When is a trace a transmission line?
When must you treat a PCB trace as a transmission line?
| Level | ● screening |
| Track | SI & high-speed |
| Really testing | Rise time, not clock frequency. |
Free full answer — one of 12 questions answered in full on this site.
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Say this first: When the trace delay is more than about 1/5–1/6 of the signal rise time. FR4 delay is ~150–180 ps/in, so a 1 ns edge makes anything over ~1 inch a transmission line, and a 100 ps edge anything over ~0.1 inch. It's the edge, not the clock rate: a 1 MHz clock with 1 ns edges still needs termination.
Numbers to quote: v = c/√Dk ≈ 6 in/ns in FR4; Len_max[in] ≈ RT[ns]; BW ≈ 0.35/RT.
Going deeper
Why one-sixth. If the round trip (2·TD) is shorter than about a third of the rise time, the reflections settle while the edge is still rising and blend into it. Longer than that, they show up as steps and ringing.
Worked examples.
- A microcontroller GPIO with 3 ns edges: critical length ≈ 3 inches in FR4. Most traces on a small board are fine.
- A DDR data line with ~100 ps edges: ≈ 0.1 inch. Every trace is a transmission line.
- A "slow" 1 MHz SPI clock from a fast FPGA pin with 0.5 ns edges: ≈ 0.5 inch. It still needs a series resistor.
Where people go wrong
- Answering with the clock frequency.
- Using a datasheet's typical rise time — fast corners and newer silicon are faster.
- Forgetting that the probe and scope must be fast enough to show the problem.
More like this in the book
This is SI-01 from Hardware Engineer Interview Questions. The book has 16 questions on signal integrity & transmission lines and 141 in all, each answered the same way: what to say first, how to explain it, the numbers worth quoting and the follow-ups that come next.
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